Changes in Intel’s hiring documentation have revealed what appears to be the first sign of the fact that the chip maker has delayed its 7 nm process to 2022. The 7nm node has been referred to, many times, as the end of conventional process technology and, quite repeatedly, the start of the road where physics will start to break down (we will go into detail on this below). Quite understandably, Intel has started to slow down its shrink schedule to milk the existing nodes for a bit longer and most of all – buy it precious time. It is with this somewhat stark backdrop in mind that we will look at this new development.
Advert pops up stating that Intel’s 7nm node has been delayed to 2022 – Will TSMC & other Pure Play foundries beat it to the process?
Motley Fool’s Ashraf Eassa was the first to spot that an Intel job advert looking for a processor designer had changed its time frame to 2022 from 2020 so the advert read:
“ The India Lab specifically, in collaboration with MRL-US and Intel product architecture teams worldwide, will spearhead the research and advanced development of Microprocessor Cores in the 2022 and beyond timeframe. By conceiving of and prototyping radical approaches, the Lab will aim to deliver much greater CPU power and area efficiency while still delivering industry-leading performance. The microarchitecture and design of these advanced CPUs will be aggressively co-optimized with Intel’s sub-10nm technology nodes deep into the next decade.”
Remember that pesky thing called Moore’s law? Well, all vestiges of that have been going out of the window with recent announcements. The Moore’s law cycle was initially stated to be a 1 year cycle, in the recent past it was a 2 year cycle. With the announcement of Kaby Lake however, the time span increased even more: tick tock became tick tock tock. With the 10nm process, Intel expects to bring out three iterations of 10nm, namely 10nm, 10nm+ and 10nm ++. If we are to believe this advert then Intel should enter volume production of 10nm in 2017 with the final micro architecture landing in 2020 (10nm for 2017-2018, 10nm+ for 2018-2019 and 10nm++ for 2019-2020).
Why physics starts to break down at near atomic sizes; the short version
Its very clear that the company is going to face a lot of problems as we move towards 7nm. People keep on saying that “physics is going to break down” at this scale – but what that does that mean really? Well, the building block of computer processors is the transistor. Which is nothing more than a gate which either allows electrons to pass – or doesn’t depending on the state. When we talk about the process node getting smaller – its actually these gates which are getting smaller. A gate below 7nm will be just a few silicon atoms thick (1nm has a about two silicon atoms but the process name does not correspond directly to the size of the gate).
At this point, you are probably wondering so what is the big deal? Those who remember elementary physics will recall that an atom is quite a big larger than an electron and as long as its bigger than an electron its good right? not exactly. This is where quantum mechanics step in. You might have heard that it is physically impossible to know the precise location of any given electron at any given time. What you can have are locations where the electron is probably located (this probability is 95% within the orbital cloud but approaches zero as you move further away, but never actually touches zero!).
When dealing with gates this small an interesting phenomenon begins to occur – the electron can simply chose to be on the other side of the gate; in other words they can effectively tunnel through the closed transistor and appear on the other side. And when you are talking about logic sensitive circuits you can’t have closed gates leaking electricity.
There are of course ways to get around this ranging from the choice of the substrate to the design of the transistor. Interestingly however, TSMC has recently revealed that it is right on track to deliver the 7nm process in 2018 which raises some very interesting questions: is Intel, the chipzilla who has dominated process advances for more than a decade finally falling behind to competition? Well, its a little more complicated than that.
Simon Wang, director of business development at TSMC stated that the company is aiming to go into volume production at 7 nanometers in the first quarter of 2018. It is only a year after the next generation, 10 nanometer, is expected to start generating revenue. Other pure play foundries like Samsung and Globalfoundries will also be following soon behind. It would look like someone forgot to tell them about physics because they don’t seem to be having a problem with it – so what’s wrong with Intel?
Understanding how foundries name their process nodes: Intel’s 10nm versus TSMC 10nm and beyond
The answer lies in the fact that Intel’s naming standards and TSMC’s naming standards are drastically different. Intel’s processes use the same backbone as the advertised node (a 14nm process will use a 14nm backbone) while as all pure play foundries use a mixture of process technologies. TSMC’s 16nm FinFET tech for example uses a 20nm backbone (BEOL). So it is almost a certainty that they will be using a 14nm BEOL for their ’10nm finfet’ node.
Let me explain a bit further, the process names that foundries use have now become more or less marketing material and not accurate physical descriptions of the node (except maybe in the case of Intel). Simply marketing a node as 7nm FinFET or 10nm FinFET does not make it a true 7nm or 10nm node respectively. I think the most relevant benchmark in this case (in my attempt to explain the point) is that of the Transistor Gate Pitch. This is the measure which is usually a very good indicator of the “true” node that a foundry might be using.
|Intel 22nm||Intel 14nm||TSMC 16nm||Samsung 14nm|
|Transistor Fin Pitch||60nm||42nm||48nm||48nm|
|Transistor Gate Pitch||90nm||70nm||90nm||84nm|
|SRAM Cell Area||.1080um²||.0588²||.0700²||.0645²|
To give a starting reference point, the Transistor Gate Pitch of a ‘true’ 22nm node is 90nm (or 45nm if you are measuring in half pitch). The Intel 22nm node, had a transistor gate half pitch of exactly 45 nm. In comparison, the transistor gate pitch of all 14nm/16nm FinFET nodes out there have a transistor gate pitch of ~90nm. This means that physically speaking, these processes are actually equal to Intel’s 22nm node. The correct physical description of the 14nm/16nm FinFET node from TSMC/GloFo and Samsung would be 20nm with FinFETs. But hey, since you are getting a performance advantage from going FinFET (over planar) at the same physical step, why not brand it as a lower node right? It’s not like most of the market can tell which is which.
Now let’s talk about Intel’s 14nm with FinFETs node. A simple calculation shows us that if a 22nm node has a Transistor Gate Pitch of 90nm, a true 14nm node with proper physical scaling should have a transistor gate pitch scaling (shrinkage) of more than more than 63%. That said, Intel has introduced 14nm with FinFETs and unlike the pure play foundries out there, it is not the same physical node as 22nm. Intel was able to achieve a shrink of roughly 30-40% over the 63% ideal shrink (Intel Transistor Gate Half Pitch for 14nm FinFET is 35nm) which while not perfect, is much closer to a true 14nm node than any of its competitors out there which are clearly 20nm and higher nodes.
So here is the thing, to truly make sense of Intel’s standing in the foundry market, and to ascertain whether or not it has lost any real industry advantage – we must put aside the cloak of invisibility marketing material and judge it on a basis of apples to apples. When TSMC says that it will be shifting to 10nm by next year – what it really means is that it will be shifting to the Transistor Gate Half Pitch measure of somewhere in the vicinity of 35nm – this is something Intel achieved last year. In other words, it will be using a 14nm back end of line (BEOL) but because the addition of FinFETs gives it a performance gain that a shift to 10nm planar would give – they call it 10nm FinFET process.
Investigating the shift of foundries to EUV for 7nm and beyond
Here is the catch though, TSMC claims that it will be shifting to Extreme Ultraviolet Lithography after the 10nm process and claims to be one of the first foundries to deploy EUV. Conventionally speaking the capabilities of the laser used can be calculated by the simple formulae of dividing the wavelength by 2. Since EUV has a wavelength of 13.5nm it can easily imprint wafers on the 7nm process (the theoretical limit is 6.75nm, easily extendable up to 5nm with tricks such as multi patterning). So how much of that is real?
Approximately two years ago, ASML and TSMC recently achieved a landmark goal by using an EUV scanner to produce more than 1000 wafers. The wafers were manufactured by using the NXE:3300B system by ASML holding and was done during the duration of exactly one day. TSMC already has two such systems in their foundry and plans to add as many as 2 more for the targeted output of 1000 wafers per day (sustained) at much higher than 90 Watts.
Now here is the thing, the scanners originally used for testing were operating at 90W power, and should have been replaced with 3350B models running at 125W and ideally the factories should be capable of 250W production by, well, this year.
Now let’s talk about Intel. The company has already stated that it does not need to use EUV for 10nm and plans to use them for nodes smaller than 10nm (although to be honest, they have been saying that ever since the 45nm node) – and you can be sure that if Intel switches to EUV, the process lead it has been enjoying for so long will hold (regardless of what the marketed names of the node might indicate). Although the customers of ASML are a secret, Intel is pretty much a no brainier considering their huge stake in the company. But if this recent advert is to be believed, it does not look like that will be happening (or happening at a date later than the others).
The demise of Intel’s process lead has always been greatly exaggerated
Conclusion: Many analysts have been pointing to the fact that Intel had problems shifting to the 14nm node and 10nm and 7nm are going to be only harder, but as I have already explained in the article, that trouble was due to the process being much smaller than everyone else and not at all comparable to TSMC’s 16nm FinFET node – which is really 20nm with FinFETs physically speaking.
This is why, at the very end of the article, I will give my opinion: It is entirely possible that 7nm wont land till 2021/2022 (considering the PAO cadence, 10nm will stay till 2020 at the very least) and it is also very much possible that you will see process nodes being marketed as 7nm by various foundries before Intel. But what is not possible (or rather highly improbable) is that Intel loses its process lead in terms of the actual physical node. Because for that to happen we have to assume that they wont be making the shift to EUV along with others and considering Intel has the largest stake (14.37%) in the company that produces the EUV scanners: ASML Holdings, it seems very very unlikely.
The simple fact of the matter is that Intel has never cared about beating the foundries on the basis of marketing material – but it has consistently beaten every other foundry to process shrinks in terms of their physical size. Apart from this advert, I see no change in any of the fundamental variables that might indicate that this will not be true for the years to come. Intel’s greatest rival has always been, and remains, the laws of physics.